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?2006 silicon storage technology, inc. s71249-07-eol 02/08 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. eol data sheet 16 mbit (x8/x16) dual-bank flash memory sst36vf1601c / sst36vf1602c features: ? organized as 1m x16 or 2m x8 ? dual bank architecture ? 16 mbit bottom sector protection - sst36vf1601c: 12 mbit + 4 mbit ? 16 mbit top sector protection - sst36vf1602c: 4 mbit + 12 mbit ? single 2.7-3.6v for read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 6 ma typical ? standby current: 4 a typical ? auto low power mode: 4 a typical ? hardware sector protection/wp# input pin ? protects the 4 outermost sectors (8 kword) in the larger bank by driving wp# low and unprotects by driving wp# high ? hardware reset pin (rst#) ? resets the internal state machine to reading array data ? byte# pin ? selects 8-bit or 16-bit mode ? sector-erase capability ? uniform 2 kword sectors ? chip-erase capability ? block-erase capability ? uniform 32 kword blocks ? erase-suspend / erase-resume capabilities ? security id feature ? sst: 128 bits ? user: 128 bits ? fast read access time ? 70 ns ? latched address and data ? fast erase and program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin ? cmos i/o compatibility ? conforms to common flash memory interface (cfi) ? jedec standards ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-lead tsop (12mm x 20mm) ? non-pb (lead-free) packages available ? all non-pb (lead-free) devices are rohs compliant product description the sst36vf1601c and sst36vf1602c are 1m x16 or 2m x8 cmos read/write flash memory manufactured with sst?s proprietary, high performance cmos super- flash technology. the split-gate cell design and thick oxide tunneling injector at tain better reliabilit y and manufacturabil- ity compared with alternate approaches. the devices write (program or erase) with a 2.7-3.6v power supply and con- form to jedec standard pinouts for x8/x16 memories. featuring high performance program, these devices pro- vide a typical program time of 7 sec and use the toggle bit, data# polling, or ry/by# to detect the completion of the program or erase operation. to protect against inad- vertent write, the devices have on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. these devices are suited for applications that require con- venient and economical updating of program, configura- tion, or data memory. for all system applications, the devices significantly improve performance and reliability, while lowering power consumption. since for any given voltage range, the superflash technology uses less cur- rent to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. sst36vf1601c / 1602c16mb (x8/x16) dual-bank flash memory
2 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. to meet high-density, surface-mount requirements, these devices are offered in 48-ball tfbga and 48-lead tsop packages. see figures 5 and 6 for pin assignments. device operation memory operation functions are initiated using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, which- ever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. auto low power mode these devices also have the auto lower power mode which puts them in a near standby mode within 500 ns after data has been accessed with a valid read operation. this reduces the i dd active read current to 4 a typically. while ce# is low, the devices exit auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. read operation the read operation is controlled by ce# and oe#; both have to be low for the system to obtain data from the out- puts. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in a high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 7). program operation these devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the byte# pin. before programming, one must ensure that the sector which is being programmed is fully erased. the program operation is accomplished in three steps: 1. software data protection is initiated using the three-byte load sequence. 2. address and data are loaded. during the program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. 3. the internal program oper ation is initiated after the rising edge of the fourth we# or ce#, which- ever occurs first. the program operation, once ini- tiated, will be completed typically within 7 s. see figures 8 and 9 for we# and ce# controlled program operation timing diagrams and figure 23 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during an internal program operation are ignored. sector- (block-) erase operation these devices offer both sector-erase and block-erase operations. these operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. the sector architecture is based on a uniform sector size of 2 kword. the block-erase mode is based on a uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with a sector- erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by execut- ing a six-byte command sequence with block-erase com- mand (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the inter- nal erase operation begins after the sixth we# pulse. any commands issued during the sector- or block-erase opera- tion are ignored except erase-suspend and erase- resume. see figures 13 and 14 for timing waveforms.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 3 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 chip-erase operation the devices provide a chip-erase operation, which allows the user to erase all sectors/blocks to the ?1? state. this is useful when a device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. any com- mands issued during the chip-erase operation are ignored. see table 5 for the command sequence, figure 12 for timing diagram, and figure 27 for the flowchart. when wp# is low, any attempt to chip-erase will be ignored. erase-suspend/erase-r esume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sect ors/blocks will output dq 2 tog- gling and dq 6 at ?1?. while in erase-suspend mode, a pro- gram operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended, the system must issue an erase-resume command. the operation is executed by issuing a one-byte command sequence with erase resume command (30h) at any address in the one-byte sequence. write operation status detection these devices provide one hardware and two software means to detect the completion of a write (program or erase) cycle in order to optimize the system write cycle time. the hardware detection uses the ready/busy# (ry/ by#) output pin. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), a data# polling (dq 7 ), or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the write cycle has completed, other- wise the rejection is valid. ready/busy# (ry/by#) the devices include a ready/b usy# (ry/by#) output sig- nal. ry/by# is an open drain output pin that indicates whether an erase or program operation is in progress. since ry/by# is an open drain output, it allows several devices to be tied in parallel to v dd via an external pull-up resistor. after the rising edge of the final we# pulse in the command sequence, the ry/by# status is valid. when ry/by# is actively pulled low, it indicates that an erase or program operation is in progress. when ry/by# is high (ready), the devices may be read or left in standby mode. byte/word (byte#) the device includes a byte# pin to control whether the device data i/o pins operate x8 or x16. if the byte# pin is at logic ?1? (v ih ) the device is in x16 data configuration: all data i/0 pins dq 0 -dq 15 are active and controlled by ce# and oe#. if the byte# pin is at logic ?0?, the device is in x8 data con- figuration: only data i/o pins dq 0 -dq 7 are active and con- trolled by ce# and oe#. the remaining data pins dq 8 - dq 14 are at hi-z, while pin dq 15 is used as the address input a -1 for the least significant bit of the address bus. data# polling (dq 7 ) when the devices are in an internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 10 for data# poll- ing (dq 7 ) timing diagram and figure 24 for a flowchart.
4 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of the fourth we# (or ce#) pulse for program operations. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-sus- pended sector/block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bit information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of a write operation. see figure 11 for toggle bit timing diagram and figure 24 for a flowchart. note: dq 7, dq 6, and dq 2 require a valid address when reading status information. data protection the devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. hardware block protection the devices provide hardware block protection which pro- tects the outermost 8 kword in the larger bank. the block is protected when wp# is held low. see figures 1, 2, 3, and 4 for block-protection location. a user can disable block prot ection by driving wp# high. this allows data to be erased or programmed into the pro- tected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. hardware reset (rst#) the rst# pin provides a hardware method of resetting the devices to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode (see figure 20). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 19). the erase operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) these devices provide the jedec standard software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, provid- ing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of the six-byte sequence. the devices are shipped with the software data protection permanently enabled. see table 5 for the spe- cific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih, but no other value during any sdp command sequence. table 1: w rite o peration s tatus status dq 7 dq 6 dq 2 ry/by# normal operation standard program dq7# toggle no toggle 0 standard erase 0 toggle toggle 0 erase- suspend mode read from erase suspended sector/block 1 1 toggle 1 read from non-erase suspended sector/block data data data 1 program dq7# toggle no toggle 0 t1.2 1249
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 5 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 common flash memory interface (cfi) these devices also contain the cfi information to describe the characteristics of the devices. in order to enter the cfi query mode, the system must write the three-byte sequence, same as the software id entry com- mand with 98h (cfi query command) to address 555h in the last byte sequence. see figure 16 for cfi entry and read timing diagram. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 6 through 8. the system must write the cfi exit command to return to read mode from the cfi query mode. security id the sst36vf160xc devices offer a 256-bit security id space. the secure id space is divided into two 128-bit seg- ments?one factory programmed segment and one user programmed segment. the first segment is programmed and locked at sst with a unique, 128-bit number. the user segment is left un-programmed for the customer to pro- gram as desired. to program the user segment of the security id, the user must use the security id program command. end-of-write status is checked by reading the toggle bits. data# polling is not used for security id end-of- write detection. once programming is complete, the sec id should be locked using the user sec id program lock- out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, nei- ther sec id segment can be erased. the secure id space can be queried by executing a three-byte command sequence with query sec id command (88h) at address 555h in the last byte sequence. see figure 18 for timing diagram. to exit this mode, the exit sec id command should be executed. refer to table 5 for more details. product identification the product identification mode identifies the devices and manufacturer. for details, see table 2 for software opera- tion, figure 15 for the software id entry and read timing diagram and figure 25 for the software id entry command sequence flowchart. the addresses a 19 and a 18 indicate a bank address. when the addressed bank is switched to product identification mode, it is possible to read another address from the same bank without issuing a new soft- ware id entry command. note: bk = bank address (a 19 -a 18 ) product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that appar- ently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 5 for the software command code, fig- ure 17 for timing waveform and figure 26 for a flowchart. table 2: p roduct i dentification address data manufacturer?s id bk0000h 00bfh device id sst36vf1601c bk0001h 734bh sst36vf1602c bk0001h 734ah t2.0 1249 1249 b1.0 superflash memory 12 mbit bank i/o buffers superflash memory 4 mbit bank memory address dq 15 /a -1 - dq 0 ce# wp# we# oe# control logic rst# byte# ry/by# address buffers (8 kword sector protection) f unctional b lock d iagram
6 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 1: sst36vf1601c, 1m x 16 d ual -b ank f lash m emory o rganization fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 0ffffh 08000h block 1 07fffh 02000h 01fffh 00000h block 0 bank 1 bottom sector protection; 32 kword blocks; 2 kword sectors 8 kword sector protection (4-2 kword sectors) 1249 f01.0 note: the address input range in x16 mode (byte#=v ih ) is a 19 -a 0
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 7 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 2: sst36vf1601c, 2m x 8 d ual -b ank f lash m emory o rganization 1fffffh 1f0000h block 31 1effffh 1e0000h block 30 1dffffh 1d0000h block 29 1cffffh 1c0000h block 28 1bffffh 1b0000h block 27 1affffh 1a0000h block 26 19ffffh 190000h block 25 18ffffh 180000h block 24 bank 2 17ffffh 170000h block 23 16ffffh 160000h block 22 15ffffh 150000h block 21 14ffffh 140000h block 20 13ffffh 130000h block 19 12ffffh 120000h block 18 11ffffh 110000h block 17 10ffffh 100000h block 16 0fffffh 0f0000h block 15 0effffh 0e0000h block 14 0dffffh 0d0000h block 13 0cffffh 0c0000h block 12 0bffffh 0b0000h block 11 0affffh 0a0000h block 10 09ffffh 090000h block 9 08ffffh 080000h block 8 07ffffh 070000h block 7 06ffffh 060000h block 6 05ffffh 050000h block 5 04ffffh 040000h block 4 03ffffh 030000h block 3 02ffffh 020000h block 2 01ffffh 010000h block 1 00ffffh 004000h 003fffh 000000h block 0 bank 1 bottom sector protection; 64 kbyte blocks; 4 kbyte sectors 16 kbyte sector protection (4-4 kbyte sectors) 1249 f01b.0 note: the address input range in x8 mode (byte#=v il ) is a 19 -a -1
8 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 3: sst36vf1602c, 1m x 16 d ual -b ank f lash m emory o rganization top block protection; 32 kword blocks; 2 kword sectors fffffh fe000h fdfffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 bank 2 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 0ffffh 08000h block 1 07fffh 00000h block 0 bank 1 8 kword block protection (4 - 2 kword sectors) 1249 f02.0 note: the address input range in x16 mode (byte#=v ih ) is a 19 -a 0
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 9 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 4: sst36vf1602c, 2m x 8 d ual -b ank f lash m emory o rganization top block protection; 64 kbyte blocks; 4 kbyte sectors block 31 block 30 block 29 block 28 block 27 block 26 block 25 block 24 block 23 block 22 block 21 block 20 block 19 block 18 block 17 block 16 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 bank 2 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 bank 1 16 kbyte block protection (4 - 4 kbyte sectors) 1249 f02b.0 1fbfffh 1f0000h 1fffffh 1fc000h 1effffh 1e0000h 1dffffh 1d0000h 1cffffh 1c0000h 1bffffh 1b0000h 1affffh 1a0000h 19ffffh 190000h 18ffffh 180000h 17ffffh 170000h 16ffffh 160000h 15ffffh 150000h 14ffffh 140000h 13ffffh 130000h 12ffffh 120000h 11ffffh 110000h 10ffffh 100000h 0fffffh 0f0000h 0effffh 0e0000h 0dffffh 0d0000h 0cffffh 0c0000h 0bffffh 0b0000h 0affffh 0a0000h 09ffffh 090000h 08ffffh 080000h 07ffffh 070000h 06ffffh 060000h 05ffffh 050000h 04ffffh 040000h 03ffffh 030000h 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h note: the address input range in x8 mode (byte#=v il ) is a 19 -a -1
10 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 5: p in a ssignments for 48- ball tfbga (6 mm x 8 mm ) figure 6: p in a ssignments for 48- lead tsop (12 mm x 20 mm ) a13 a9 we# ry/by# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 byte# dq14 dq12 dq10 dq8 ce# note* dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1249 48-tfbga p1.0 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h note* = dq 15 /a -1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1249 48-tsop p2.0 standard pinout top view die up a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# rst# nc wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# v ss dq15/a -1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 11 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 3: p in d escription symbol name functions a 19 -a 0 address inputs to provide memory addresses. during sector-erase and hardware sector protection, a 19 -a 11 address lines will select the sector. during block-erase a 19 -a 15 address lines will select the block. dq 14 -dq 0 data input/output to output data during read cycles and receive input data during write cycles data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. dq 15 /a -1 data input/output and lbs address dq 15 is used as data i/o pin when in x16 mode (byte# = ?1?) a -1 is used as the lsb address pin when in x8 mode (byte# = ?0?) ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers we# write enable to control the write operations rst# hardware reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k - 100k pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. wp# write protect to protect and unprotect top or bo ttom 8 kword (4 outermost sectors) from erase or program operation. byte# word/byte configuration to select 8-bit or 16-bit mode. v dd power supply to provide 2.7-3.6v power supply voltage v ss ground nc no connection unconnected pins t3.2 1249 table 4: o peration m odes s election mode 1 1. rst# = v ih for all described operation modes ce# oe# we# dq 7 -dq 0 dq 15 -dq 8 address byte# = v ih byte# = v il read v il v il v ih d out d out dq 14 -dq 8 = high z a in program v il v ih v il d in d in dq 15 = a -1 a in erase v il v ih v il x 2 2. x can be v il or v ih , but no other value. x high z sector or block address, 555h for chip-erase standby v ih x x high z high z high z x write inhibit x v il x high z / d out high z / d out high z x xxv ih high z / d out high z / d out high z x product identification software mode v il v il v ih manufacturer?s id (bfh) manufacturer?s id (00h) high z see table 5 device id 3 3. device id = sst36vf1601c = 734bh, sst36vf1602c = 734ah device id 3 high z t4.2 1249
12 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 5: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 30h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 50h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user security id program 555h aah 2aah 55h 555h a5h siwa 6 data user security id program lock-out 7 555h aah 2aah 55h 555h 85h xxh 0000h software id entry 8 555h aah 2aah 55h bk x 9 555h 90h cfi query entry 555h aah 2aah 55h bk x 9 555h 98h software id exit/ cfi exit/ sec id exit 10,11 555h aah 2aah 55h 555h f0h software id exit/ cfi exit/ sec id exit 10,11 xxh f0h t5.6 1249 1. address format a 11 -a 0 (hex), addresses a 19 -a 12 can be v il or v ih , but no other value, for the command sequence when in x16 mode. when in x8 mode, addresses a 19 -a 12, address a -1 and dq 14 -dq 8 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word/byte address 4. sa x for sector-erase; uses a 19 -a 11 address lines ba x for block-erase; uses a 19 -a 15 address lines 5. for sst36vf1601c, sst id is read with a 3 = 0 (address range = 00000h to 00007h), user id is read with a 3 = 1 (address range = 00010h to 00017h). lock status is read with a 7 -a 0 = 000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. for sst36vf1602c, sst id is read with a 3 = 0 (address range = c0000h to c0007h), user id is read with a 3 = 1 (address range = c0010h to c0017h). lock status is read with a 7 -a 0 = c00ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 6. siwa = user security id program word/byte address for sst36vf1601c, valid word-addresses for user sec id are from 00010h-00017h. for sst36vf1602c, valid word-addresses for user sec id are from c0010h-c0017h. all 4 cycles of user security id program and program lock- out must be completed before going back to read-array mode. 7. the user security id program lock-out command must be executed in x16 mode (byte#=v ih ). 8. the device does not remain in software product identification mode if powered down. 9. a 19 and a 18 = bk x (bank address): address of the bank that is switched to software id/cfi mode with a 17 -a 1 = 0;sst manufacturer?s id = 00bfh, is read with a 0 = 0 sst36vf1601c device id = 734bh, is read with a 0 = 1 sst36vf1602c device id = 734ah, is read with a 0 = 1 10. both software id exit operations are equivalent 11. if users never lock after programming, user sec id can be pr ogrammed over the previously unpr ogrammed bits (data=1) using th e user sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). for sst36vf1601c, valid word-addresses for user sec id are from 00010h-00017h. for sst36vf1602c, valid word-addresses for user sec id are from c0010h-c0017h.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 13 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 6: cfi q uery i dentification s tring 1 address x16 mode address x8 mode data 2 description 10h 20h 0051h query unique ascii string ?qry? 11h 22h 0052h 12h 24h 0059h 13h 26h 0001h primary oem command set 14h 28h 0007h 15h 2ah 0000h address for primary extended table 16h 2ch 0000h 17h 2eh 0000h alternate oem command set (00h = none exists) 18h 30h 0000h 19h 32h 0000h address for alternate oem extended table (00h = none exits) 1ah 34h 0000h t6.2 1249 1. refer to cfi publication 100 for more details. 2. in x8 mode, only the lower byte of data is output. table 7: s ystem i nterface i nformation address x16 mode address x8 mode data 1 1. in x8 mode, only the lower byte of data is output. description 1bh 36h 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 38h 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 3ah 0000h v pp min (00h = no v pp pin) 1eh 3ch 0000h v pp max (00h = no v pp pin) 1fh 3eh 0004h typical time out for program 2 n s (2 4 = 16 s) 20h 40h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 42h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 44h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 46h 0001h maximum time out for program 2 n times typical (2 1 x 2 4 = 32 s) 24h 48h 0000h maximum time out for buffer program 2 n times typical 25h 4ah 0001h maximum time out for individual sector-/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 4ch 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t7.3 1249
14 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 8: d evice g eometry i nformation address x16 mode address x8 mode data 1 description 27h 4eh 0015h device size = 2 n bytes (15h = 21; 2 21 = 2 mbyte) 28h 50h 0002h flash device interface description; 0002h = x8/x16 asynchronous interface 29h 52h 0000h 2ah 54h 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 56h 0000h 2ch 58h 0002h number of erase sector /block sizes supported by device 2dh 5ah 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 5ch 0003h y = 1023 + 1 = 1024 sectors (03ffh = 1023) 2fh 5eh 0008h 30h 60h 0000h z = 8 x 256 bytes = 2 kbyte/sector (0008h = 8) 31h 62h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 64h 0000h y = 31 + 1 = 32 blocks (001fh = 31) 33h 66h 0000h 34h 68h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t8.3 1249 1. in x8 mode, only the lower byte of data is output.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 15 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma o perating r ange : range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 21 and 22
16 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 9: dc o perating c haracteristics v dd = 2.7-3.6v symbol parameter limits test conditions freq min max units i dd 1 active v dd current read 5 mhz 15 ma ce#=oe#=v il, we#=v ih, all i/os open 1 mhz 10 ma program and erase 40 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#, rst#=v dd 0.3v i alp auto low power v dd current 20 a ce#=0.1v, v dd =v dd max we#=v dd -0.1v address inputs=0.1v or v dd -0.1v i rt reset v dd current 20 a rst#=gnd i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# pin 10 a wp#=gnd to v dd , v dd =v dd max rst#=gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t9.3 1249 1. address input = v ilt /v iht, v dd =v dd max (see figure 21) table 10: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t10.0 1249 table 11: c apacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 10 pf c in 1 input capacitance v in = 0v 10 pf t11.0 1249 table 12: r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t12.0 1249
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 17 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 ac characteristics table 13: r ead c ycle t iming p arameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t13.0 1249 table 14: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp program time 10 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t es erase-suspend latency 20 s t by 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. ry/by# delay time 90 ns t br 1 bus recovery time 0 s t14.1 1249
18 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 7: r ead c ycle t iming d iagram figure 8: we# c ontrolled p rogram c ycle t iming d iagram 1249 f04.0 addresses dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1249 f05.1 addresses dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t bp ry/by# t by t br note: x can be v il or v ih , but no other value. valid
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 19 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 9: ce# c ontrolled p rogram c ycle t iming d iagram figure 10: d ata # p olling t iming d iagram 1249 f06.1 addresses dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# ce# bp ry/by# t by t br note: x can be v il or v ih , but no other value. valid 1249 f07.1 address a 19-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes ry/by# t by
20 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 11: t oggle b it t iming d iagram figure 12: we# c ontrolled c hip -e rase t iming d iagram 1249 f08.0 addresses dq 6 we# oe# ce# t oe t oeh t ce two read cycles with same outputs valid data t br 1249 f09.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 14) x can be v il or v ih , but no other value. ry/by# t by valid t br
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 21 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 13: we# c ontrolled b lock -e rase t iming d iagram figure 14: we# c ontrolled s ector -e rase t iming d iagram 1249 f10.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 14) ba x = block address x can be v il or v ih , but no other value. ry/by# valid t by t br 1249 f11.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 14) sa x = sector address x can be v il or v ih , but no other value. ry/by# t by t br valid
22 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 15: s oftware id e ntry and r ead figure 16: cfi e ntry and r ead 1249 f12.1 addresses t ida dq 15-0 we# device id = 734bh for sst36vf1601c and 734ah for sst36vf1602c 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih , but no other value. 1249 f13.1 addresses t ida dq 15-0 we# 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 23 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 17: s oftware id e xit /cfi e xit figure 18: s ec id e ntry 1249 f14.1 addresses dq 15-0 t ida t wp t wph we# 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value. 1249 f15.1 address a 19-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih , but no other value.
24 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 19: rst# t iming d iagram (w hen no internal operation is in progress ) figure 20: rst# t iming d iagram (d uring s ector - or b lock -e rase operation ) 1249 f16.0 ry/by# 0v rst# ce#/oe# t rp t rhr 1249 f17.0 ry/by# ce# oe# t rp t ry t br rst#
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 25 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 21: ac i nput /o utput r eference w aveforms figure 22: a t est l oad e xample 1249 f18.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1249 f19.0 to tester to dut c l
26 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 23: p rogram a lgorithm 1249 f20.2 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 27 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 24: w ait o ptions 1249 f21.1 wait t bp , t sce , t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
28 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 25: s oftware p roduct id/cfi/s ec id e ntry c ommand f lowcharts 1249 f22.2 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id x can be v il or v ih , but no other value
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 29 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 26: s oftware p roduct id/cfi/s ec id e xit c ommand f lowcharts 1249 f23.1 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih, but no other value
30 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 figure 27: e rase c ommand s equence 1249 f24.1 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 31 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 product ordering information valid combinations for sst36vf1601c sst36vf1601c-70-4c-b3ke SST36VF1601C-70-4C-EKe sst36vf1601c-70-4i-b3ke sst36vf1601c-70-4i-eke valid combinations for sst36vf1602c sst36vf1602c-70-4c-b3ke sst36vf1602c-70-4c-eke sst36vf1602c-70-4i-b3ke sst36vf1602c-70-4i-eke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type b3 = tfbga (6mm x 8mm) e =tsop (type 1, die up, 12mm x 20mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns bank split 1 = 12 mbit + 4 mbit 2 = 4 mbit + 12 mbit device density 160 = 1mbit x16 or 2mbit x8 voltage v = 2.7-3.6v product series 36 = dual-bank flash memory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 36 vf 1601c - 70 - 4c - b3k e xx x x xxx x x - xxx -xx -xx x x
32 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 packaging diagrams 48- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c 33 ?2006 silicon storage technology, inc. s71249-07-eol 02/08 48- lead t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0?- 5? detail pin # 1 identifier 0. 50 bsc
34 eol data sheet 16 mbit dual-bank flash memory sst36vf1601c / sst36vf1602c ?2006 silicon storage technology, inc. s71249-07-eol 02/08 table 15: r evision h istory number description date 00 ? initial release of data sheet oct 2003 01 ? 2004 data book ? updated b3k package diagram ? added mpns for ek package dec 2003 02 ? clarified chip-erase operation on page 3 ? added x8 mode address maps in figure 2 and figure 4 ? added footnote for rst# to table 4 ? changes to table 5 on page 12 ? corrected word/byte program command name ? updated footnotes 1, 5, 6, and 11 for x8 mode and updated sec id address ? added footnote 7 for the user security id program lock-out command ? added x8 mode addresses in cfi tables 6, 7, and 8 and a footnote ? corrected x8/x16 cfi value in table 8 on page 14 ? changes to table 9 on page 16 ? added the i liw parameter ? corrected the test conditions for irt from rst#=v ss 0.3v to rst#=gnd ? corrected the address input from v il /v ih to v ilt /v iht and added a figure reference feb 2004 03 ? removed chip-erase from the ?concurrent read/write operation? table footnote ? corrected the address lines for sector-erase from a 19 -a 10 to a 19 -a 11 in table 3 and ta bl e 5 ? updated software command sequence addresses in table 5 on page 12, timing dia- grams, and flowcharts ? changed references to word-program and byte-program to program ? clarified surface mount temperatures in ?absolute maximum stress ratings? on page 15 aug 2004 04 ? changed title of data sheet from ?concurrent superflash? to ?dual-bank flash? ? removed references to concurrent bank operations ? removed the section, ?concurrent read/write operation? from page 2 ? updated sector information in table 8, ?device geometry information? on page 14 nov 2004 05 ? reverted table 8, ?device geometry information? on page 14 to revision 03 (t8.3 1249) dec 2004 06 ? added statement that non-pb devices are rohs compliant to features section ? updated surface mount solder reflow temperature information ? removed leaded part numbers ? migrated document to a data sheet jan 2006 07 ? end of life all valid combinations in this data sheet. replacement part sst36vf160xe feb 2008 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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